Structure and layout of a fet prime cell

ABSTRACT

A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

FIELD OF THE INVENTION

The invention relates to semiconductor circuits, and more particularlyto FET (field effect transistor) circuits for microwave and RF (radiofrequency) applications.

BACKGROUND OF THE INVENTION

In general, a FET is a three-terminal device which may find use in bothmicrowave amplification and switching. The three terminals on the FETinclude a gate, source and drain. A basic FET includes a galliumarsenide (GaAs) substrate with an active layer arranged thereon. Theactive layer includes a source and a drain, with a gate arrangedtherebetween on top of the active layer. The FET may also include abackside metal on the bottom of the substrate. The backside metal may beconfigured to be in electrical communication with the source by a platedvia hole through the substrate.

In operation, a voltage signal applied to the gate creates a depletionor inversion region in the active region between the source and thedrain. This region allows current to flow between the source and thedrain, respectively. In typical microwave and RF applications, the drainis the output of the device. FETs can be structured in the form of a FETprime cell which has better frequency and power properties then thebasic FET design. The prime cell provides the gate, source, drain,substrate and wiring configuration to make an RF amplifier.

Although offering improved frequency and power characteristics, typicalFET prime cell configurations include a relatively large footprint ofthe device due to the various features of the FET prime cell spreadacross the top region of the substrate. Additionally, typical FETdesigns include the wiring related capacitance between the gate fingersto the substrate. There is also wiring related capacitance between thesource fingers and the substrate. Neither of these wiring relatedcapacitances scale with shrinking device geometry, and thus becomedifficult to improve at ever smaller device sizes. These wiring relatedcapacitances lead to a reduction in the maximum workable frequency ofthe device and thus imposes frequency limitation on the FET prime cell.

For example, FIGS. 1 and 2 show a typical FET prime cell 100. The FETprime cell 100 includes a substrate 122 with alternating or interleavedsource contacts and drain contacts, 104 and 106, respectively, arrangedthereon. Also arranged on the substrate 122 are gate fingers 102 betweenthe source contacts and drain contacts 104 and 106. The gate fingers 102are interconnected with one another by a metal ring 108. The metal ring108 forms a conductive ring around the region of the substrate 122 onwhich the gate fingers, source contacts, and drain contacts, 102, 104and 106, are arranged.

Arranged in the substrate 122 surrounding the active region of the FET100 is a shallow trench isolation 120 which is surrounded by a ringsubstrate contact 118 (e.g., the ring substrate contact 118 is arrangedadjacent and outboard of the shallow trench isolation 120). The ringsubstrate contact 118 provides electrical contact to substrate 122. Theouter-most sources 114 have the shallow trench isolation 120 arranged oneither outboard side.

Accordingly, typical FET designs also include an explicit substratecontact which leads to requiring a unique wiring of the gate. Therequired wiring is not optimal for device operation and adds anundesirable design constraint for circuit designers. Also, typicalrelated art designs cause wiring parasitics which may prevent thesubstrate from actually being at the same potential as the source.Additionally, the combination of the shallow trench isolation adjacentthe ring substrate contact may make the typical FET more susceptible tostray currents and other electrical noise.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a method of making a semiconductordevice includes forming a source and a drain in a substrate. The methodalso includes forming a gate on the substrate between the source anddrain, and forming a substrate contact in electrical contact with thesource. The method additionally includes forming an electrical contactbetween the source, drain and gate, and the substrate.

In another aspect of the invention, a semiconductor device includes asubstrate and a source and a drain arranged within the substrate. Thedevice also includes a gate formed on the substrate between the sourceand drain, and a substrate contact formed within the substrate adjacentthe source.

In yet another aspect of the invention, a semiconductor device includesa substrate, and at least two source fingers formed in the substratesubstantially parallel to one another. The device also includes at leastone drain finger formed in the substrate between the at least two sourcefingers. The device also includes at least two gate fingers formed on atop of the substrate, wherein each gate finger is arranged between theat least one drain finger and one source finger of the at least twosource fingers. The device additionally includes a substrate contactformed within the substrate and adjacent two source fingers of the atlest two source fingers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a top view of a typical FET prime cell formicrowave and RF applications;

FIG. 2 is an illustration of a cross-sectional view of a typical FETprime cell for microwave and RF applications;

FIG. 3 is an illustration of a cross-sectional view of an embodiment ofa FET prime cell in accordance with the invention;

FIG. 4 is an illustration of a top view of an embodiment of a FET primecell in accordance with the invention;

FIG. 5 is an illustration of a cross-sectional view of an embodiment ofa FET prime cell in accordance with the invention;

FIG. 6 is an illustration of a top view of an embodiment of a FET primecell in accordance with the invention; and

FIG. 7 is a flow chart of a method of manufacturing a FET prime cell inaccordance with the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In general, embodiments of the invention are directed to reducing thefootprint of a FET prime cell as well as improving speed by reducingparasitic capacitance and allowing the circuit designer greater designfreedom. An example of the invention includes eliminating a shallowtrench isolation area from between the source and a ring substratecontact, and allowing the ring substrate contact to be arranged adjacentto or abutting the source without the need for a shallow trenchisolation structure.

FIG. 3 shows an embodiment 200 of the invention without a shallowisolation trench in the substrate, and includes a ring structure makingcontact with the source. The embodiment 200 includes a substrate 202onto which is arranged an active region 204. Arranged within the activeregion 204 are a drain 206 and a source 208. The source 208 and thesubstrate 202 may be held at the same voltage potential. Arranged on theactive region 204 is a gate 210 between the drain 206 and the source208. Also arranged within the active region 204 is a ring substratecontact 212 (e.g., ring structure). The ring substrate contact 212 isarranged within the active region 204 adjacent to the source 208. Thus,the ring substrate contact 212 abuts or is adjacent to a side of thesource 208 and is capable of being in electrical contact therewithwithout an intervening nonconductive structure such as a shallow trenchisolation which would interfere with electrical contact between the ringstructure and the source (e.g., separated by a conductive material).

In one embodiment of the invention, the ring substrate contact 212 is ap+ contact placed next to the source 208 of the FET 200. Silicide thenprovides an electrical contact between the source 208 and the body oractive region 204 of the FET 200, such as, for example, forming a layerof silicide over a top surface of the source 208 and the body or activeregion 204. It should be noted that by locating the ring substratecontact 212 next to the source 208, in this fashion, it is not necessaryto have a metal contact to the active region 204.

Referring to FIG. 4, a top view of another embodiment of the inventionincludes a FET prime cell 300. The FET prime cell 300 includes a p-wellactive region 304 with the elongated source contacts 316 and draincontacts 318 arranged across the surface of the active region 304 andalternating with one another. Arranged across the top of the activeregion 304 and between each source contact and drain contact, 316 and318, are gate fingers 310. Accordingly, the source contacts 316, draincontacts 318 and gate fingers 310 are interleaved with one another onthe surface of the active region 304. Each end of each gate finger 310is connected to a gate bus 324. An end of each source contact 316 isconnected to a source bus 322, and an end of each drain contact 318 isconnected to a drain bus 320. Surrounding the active region 304 of theFET prime cell 300 is a metal ring 314.

Referring to FIG. 5, a cross-section of the FET prime cell 300 of FIG. 4is shown. As seen in the cross-section, the FET prime cell 300 includesa p-well active region 304 into which are arranged alternating elongateddrain fingers 306 and source fingers 308. Underneath each source contact316 is the source finger 308, and underneath each drain contact 318 isthe drain finger 306. Additionally, the source finger 308 and the drainfinger 306 may each include metal tabs. The source contact 316 isconnected to the source finger 308 with a metal connect 332, and thedrain contact 318 is connected to the drain finger 306 with a metalcontact 334. The drain fingers 306 and source fingers 308 include N+wells, 330 and 328, respectively.

On top of the active region 304 and between each drain finger and sourcefinger, 306 and 308, are the gate fingers 310. Adjacent to each outerside of each outer-most source finger 308 is a ring substrate contact orsubstrate contact 312 (e.g., ring structure). The ring substrate contact312 includes a p+ region formed in the p-well 304. Also in contact withthe source contact 316 in the center of the FET prime cell 300 is tab326. Accordingly, the source fingers 308 and the ring substrate contact312 are in electrical contact with one another and can be held at thesame voltage potential.

As can be seen in FIG. 5, the ring substrate contact 312 may be adjacentto or abutting against the outer-most source finger 308 in the body oractive region 304 of the FET prime cell 300. Accordingly, the ringsubstrate contact 312 may be placed in contact with the outer-mostsource finger 308, or at least in close proximity thereto withsubstantially no intervening non-conductive material which wouldinterfere with electrical contact between the ring structure and thesource. As such, the ring substrate contact 312 helps to keep the bodyor active region 304 of the FET prime cell 300 at a known voltagepotential. Additionally, such a configuration of the ring substratecontact 312 relative to the outer-most source finger 308 may also act asa collection source for stray currents. Such stray currents may beproduced by electrical noise, which may be induced from a nearby currentsource, such as, for example, another device or circuit.

It should be noted that in the examples above, the ring substratecontact may be described as completely or almost completely encirclingthe body or active region of a FET prime cell. Accordingly, abutting thering substrate contact against the outer-most source finger or adjacentthereto with substantially no intervening material such as a shallowtrench isolation remains beneficial regardless of whether the structurecompletely or incompletely encircles the active area of the FET primecell. Thus, the ring substrate contact may extend anywhere fromcompletely around the active region of the FET prime cell to any portionthereof, such as, for example, three-quarters of the way or half-wayaround the FET prime cell.

Referring to FIG. 6, a top view of an alternate embodiment of the FETprime cell 400 is shown. The FET prime cell 400 includes a body oractive region 404 which has drain contacts 418 and source contacts 416arranged thereon. The drain contacts 418 and the source contacts 416 areelongated and alternate with one another across the surface of theactive region 404. Within the surface of the active region 404underneath of the source contacts 416 are source fingers (not shown) andarranged under the drain contacts 418 in the surface of the actionregion 404 are drain fingers (not shown). Also arranged on the surfaceof the active region 404 and between the source fingers and drainfingers are gate fingers 410. The source contacts 416 are connected toone another with a source bus 422, and the gate fingers 410 areconnected to one another with gate busses 424 at either end of the gatefingers 410. The drain contacts 418 are connected to one another with adrain bus 420. Arranged within the active region 404 is a ring substratecontact 412.

The ring substrate contact 412 is arranged in the active region 404 sothat it is adjacent to and may abut the outer-most source fingers.Additionally, the ring substrate contact 412 may be arranged in theactive region 404 of the FET prime cell 400 so that it is in closeproximity to the outer-most source.

The FET prime cell 400 shown in FIG. 6 also includes a silicon tab 426which extends from the active region 404. Accordingly, if proximity of ap+ diffusion area to the gate region and the drain region needs to beoptimized, then the FET prime cell 400 incorporates the silicon tab 426which is doped p-type for the source contact 416. Note that a similarmethod may also be adopted for pFETs.

As shown in the embodiments, the ring substrate contact is arrangedwithin the active region of the FET prime cell such that it is either inclose proximity to the outer-most source fingers or abuts the sourcefingers. Additionally, because little or no current flows through thering substrate contact, it is not necessary to have any metal contact atthe ring substrate contact. Silicide provides the electrical contactbetween the source and the body.

A method of manufacturing a FET prime cell having a reduced footprintand improved speed, for example similar to the FET prime cell of FIGS.3-6, may include the steps shown in FIG. 7. For example, referring toFIG. 7 in conjunction with any of the embodiments of FIGS. 3-6, a P-wellactive region is formed in a substrate (S105). The P-well active regionsmay be formed by any of the suitable doping methods well known in theart.

Gate fingers are next formed on the substrate (S110). The gate fingersmay be formed by any of the deposition, imaging and etching methods wellknown in the art for gate formation. The gates are used as a mask whilesource/drain regions are formed having N+ wells by any of the dopingmethods well know in the art for forming source/drain regions (S115). Asubstrate contact is formed around the active region (S120). Thesubstrate contact may be formed from a conductor such as a metal and mayformed using any of the methods well known in the art for forming such aconductor in the substrate.

Fingers are formed on each of the source/drain regions (S125). Metalconnects are attached to the source/drain regions and source/draincontacts are formed in contact with the metal connects (S130). Aconductive tab may be formed in electrical contact with the sourcecontact near the center of the prime FET cell (S135) in one embodiment,having metal connects and source/drain contacts formed thereto, as well(repeat S130). Accordingly, an FET prime cell having a substrate contactis formed.

While the invention has been described in terms of exemplaryembodiments, those skilled in the art will recognize that the inventioncan be practiced with the modifications and in the spirit and scope ofthe intended claims.

1. A method of making a semiconductor device, comprising the steps of:forming a source and a drain in a substrate; forming a gate on thesubstrate between the source and drain; forming a substrate contact inelectrical contact with the source; and forming an electrical contact tothe source, drain and gate, and the substrate.
 2. The method of claim 1,further comprising arranging the source and the substrate atsubstantially the same voltage potential.
 3. The method of claim 1,further comprising forming the substrate contact in electrical contactwith the source.
 4. The method of claim 3, further comprising formingthe substrate contact in direct physical contact with the source.
 5. Themethod of claim 1, wherein the substrate contact comprises a p+ region.6. The method of claim 1, wherein the semiconductor device furthercomprises at least any of an additional source, drain, and gate.
 7. Themethod of claim 1, further comprising forming a silicon tab in contactwith the substrate contact and forming a silicide layer on a top of thesubstrate contact.
 8. The method of claim 1, wherein the substratecontact is formed to partially surround the active region.
 9. The methodof claim 8, wherein the substrate contact is formed to completelysurround an active region defined by the drain, source, and gate. 10.The method of claim 1, wherein the substrate contact is formed inelectrical contact with the source without substantially anynon-conductive material therebetween.
 11. A method of fabricating adevice, comprising the steps of: forming an active region including asource, drain and gate region; and forming a collection sourceconfigured for shielding electrical noise external to the active region.12. The method of claim 11, further comprising forming the collectionsource in electrical contact with the source region.
 13. The method ofclaim 11, further comprising forming the collection source in directphysical contact with the source region and either substantially orcompletely surrounding the active region.
 14. A semiconductor device,comprising; a substrate; a source and a drain arranged within thesubstrate; a gate formed on the substrate between the source and drain;and a substrate contact formed within the substrate in electricalcontact with the source.
 15. The semiconductor device of claim 14,further comprising the substrate contact being configured to shield thesemiconductor device from electrical noise.
 16. The semiconductor deviceof claim 14, further comprising the substrate contact being in directphysical contact with the source of the semiconductor device.
 17. Thesemiconductor device of claim 14, wherein the substrate contactcomprises a p+ region.
 18. The semiconductor device of claim 14, whereinthe source comprises a source finger and the substrate contact abutssubstantially all of one side of the source finger.
 19. Thesemiconductor device of claim 18, comprising at least two source fingersarranged within the substrate, wherein the substrate contact abuts twoof the at least two source fingers.
 20. The semiconductor device ofclaim 14, wherein the substrate contact comprises a p-type doped silicontab contacting the source and a silicide layer arranged on a top of thesubstrate contact.
 21. A semiconductor device, comprising: a substrate;at least two source fingers in the substrate substantially parallel toone another; at least one drain finger in the substrate between the atleast two source fingers; at least two gate fingers on a top of thesubstrate, wherein each gate finger is arranged between the at least onedrain finger and one source finger of the at least two source fingers;and a substrate contact within the substrate and adjacent two sourcefingers of the at least two source fingers configured to shield thesemiconductor device from electrical noise.
 22. The semiconductor deviceof claim 21, wherein the at least two gate fingers are connected to oneanother at at least one end with a gate finger bus.
 23. Thesemiconductor device of claim 21, wherein the at least two sourcefingers are connected to one another at at least one end with a sourcefinger bus.
 24. The semiconductor device of claim 21, further comprisingat least two drain fingers, wherein the at least two drain fingers areconnected to one another at least at one end with a drain finger bus.25. The semiconductor device of claim 21, wherein the substrate contactelectrically contacts two source fingers of the at least two sourcefingers.
 26. The semiconductor device of claim 21, further comprising agate finger bus electrically connecting the at least two gate fingers,wherein: the at least two source fingers comprise a source metal tabdisposed on a top of the substrate and the at least one drain fingercomprises a drain metal tab disposed on a top of the substrate, the gatefinger bus is electrically connected to the metal ring, the onlyelectrical connection to the substrate is through the source metal tab,the substrate, the at least two source fingers, the at least one drainfinger, and the at least two gate fingers are configured to amplify anRF signal.
 27. The semiconductor region of claim 21, wherein thesubstrate contact is configured to physically contact all of a side ofeach of the two source fingers of the at least two source fingers. 28.The semiconductor device of claim 21, wherein the substrate contactcomprises a p+ region.
 29. The semiconductor device of claim 21, whereinthe substrate contact comprises a p-type doped silicon tab.
 30. Thesemiconductor device of claim 21, further comprising a silicide layerarranged on top of the substrate contact.